Xilinx FIR Coefficient Configuration Implemented in ROACH Architecture

Abstract

Dynamically run time reconfigurable FIR Filter with a control logic architecture for Coefficient reload is designed and tested on a Xilinx Virtex 5 FPGA ROACH board for signal recording at the Arecibo Observatory. A filter with fixed coefficients is used as to compare it with the reconfigurable filter. The resulting control logic design and the filter can be reconfigured with any coefficient and filter type limited only by its length (filter order) or word size. Key Terms - CASPER (Collaboration for Astronomy Signal Processing and Electronics Research), Control Logic, Field Programmable Gate Array (FPGA), Finite Impulse Response (FIR) Filter, Reconfigurable Open Architecture Computing Hardware (ROACH).