Simulación digital para verificación de diseño y sus aplicaciones en el desarrollo de pruebas automatizadas

Abstract

This paper presents the digital simulator as the tool for the computerized analysis of digital logic circuits. Among the topics discussed in the study are the behaviour of digital circuits, the development of vectors to test automated equipment, the fault principle to test digital circuits and the use of models to simulate the digital logic. The logic simulator driven by events is studied in detail and some advices on how to implant a logical simulator are given.