PLAtestGA: A CNF-Satisfiability Problem for the Generation of Test Vectors for Missing Faults in VLSI Circuits

Abstract

An evolutionary algorithm (EA) approach is used in the development of a test vector generation application for single and multiple fault detection of growth faults in Programmable Logic Arrays (PLA). Three basic steps are performed during the generation of the test vectors: crossover, mutation and selection. The genetic operators are applied to the CNF-satisfiability problem for the generation of test vectors for growth faults. Once crossover and mutation have occurred, the new candidate test vectors with higher fitness function scores replace the old ones. With this scheme, population members steadily improve their fitness level with each new generation. The resulting process yields improved solutions to the problem of the PLA test vector generation.