A Hybrid Deterministic/Genetic Test Generator to Improve Fault Effectiveness and Reduce CPU Time Run

Abstract

This paper focuses on an evolutionary algorithm (EA) approach in the development of effective test vector generation for single and multiple fault detection in VLSI circuits. The genetic operators (selection, crossover, and mutation) are applied to the CNF-satisfiability problem for the generation of test vectors for growth faults in Programmable Logic Arrays (PLAs). The CNF-constraints satisfaction problem has several advantages over other approaches used for PLA testing. The method proposed eliminates the possibility of intersecting a redundant growth term with a valid candidate test vector. Deterministic procedures are used to allow the identification of untestable faults and to improve the fault coverage. This hybrid deterministic/genetic test generator helps improve fault effectiveness and reduce CPU time run. Experimental results have confirmed that the number of untestable faults identified contributed to test generation effectiveness.